Digital wireless telephone systems are becoming increasingly popular due to ever-improved performance, clarity etc. Most systems operate with multiple users, each having a wireless terminal (i.e., phone handset, laptop, etc.) and a common base station for controlling signal transmission and receipt by each of the wireless terminals.
One common protocol used in such systems is time-division multiple-access (TDMA), in which the time spectrum is divided into multiple slots of time. The time slots are shared by the multiple users (each having a unique wireless terminal) such that each user is assigned certain time slots within which to transmit and receive signals (i.e., make or receive phone calls from a handset). If there are N users, for example, then each user may be assigned every Nth time slot within which to transmit or receive data.
At fixed intervals, the base station transmits a “paging block”, which may include information pertinent to more than one terminal, such as whether a terminal is in receipt of a phone call, for example. Each paging block may have a duration of 20 milliseconds and the fixed intervals between paging blocks may range from ½ to 2 seconds, for example. All users (terminals) attempt to read (receive and decode) each paging block to determine whether in receipt of a phone call. Thus, each terminal may have certain circuit components that power up just before each paging block, in order to read that paging block, and then power down (to save power) between paging blocks (during the ½ to 2 second delay between paging blocks).
With TDMA, it is very important that each wireless terminal maintain an accurate time reference in order to turn “on” at appropriate times, i.e., before each paging block, in order to read that paging block. Wireless terminals typically have a local oscillator for producing a clock signal that is up-converted to a frequency at which to transmit and receive data. It is very important for each wireless terminal to calibrate its local oscillator such that the frequency of the output clock signal matches that of a base station reference clock signal, in order that information is transmitted and received accurately, at a precise time and at a precise radio frequency. The accurate time and frequency references must be maintained by the terminal for a time period (i.e., 20 minutes) that is much greater than the delay (i.e., ½ to 2 seconds) between consecutive paging blocks, in case, for example, a terminal is unable to read a number of consecutive paging blocks due to interference, lack of range, etc.
Calibration of the local clock signal within a wireless terminal to the base station clock signal typically occurs upon power up of the terminal and intermittently thereafter. This serves to provide an accurate frequency at which to receive and transmit signals and serves as a reference to maintain accurate time reference. It is desirable in such systems to reduce the power consumed by the circuitry in the wireless terminal both for cost reasons and so that the terminal can remain operational for as long a period of time as possible without requiring power recharging.
One prior art approach aimed at reducing the amount of power consumed by wireless terminals is shown in FIG. 1. FIG. 1 is a part block, part schematic diagram of a prior art frequency control circuit employed in wireless terminals. As will be described, the prior art frequency control circuit of FIG. 1 employs a precision, low-power digital-to-analog converter (DAC) 22, the digital input to which is updated during frequency calibration sequences. The digital input then is held between calibration sequences to maintain an accurate time reference and clock frequency, enabling other circuit elements to be powered down between paging blocks.
As shown in FIG. 1, the frequency control circuit includes a frequency control input 20, frequency control DAC 22, integrated circuit (IC) pads 24 and 28, a resistor/capacitor filter network (consisting of resistor R and capacitor C1), and a low-jitter voltage-controlled temperature-compensated crystal oscillator (VCTCXO).
During operation, frequency control input 20 receives a digital control signal along bus 9. The digital control signal may be supplied by a digital signal processor (DSP) (not shown). Frequency control input 20, in turn, provides a digital control signal along bus 21 to frequency control DAC 22. Frequency control DAC 22 conventionally converts the digital control signal to an analog signal, which analog signal is filtered by the RC filter (R, C1) before provision to low-jitter VCTCXO 26. Low-jitter VCTCXO 26, in turn, provides an adjusted frequency output signal, based on receipt of the filtered, analog control signal. The signal output will have a frequency adjusted from its center frequency of oscillation (i.e., 13 MHz).
The output signal is fed back along line 27, through pad 28, and along line 29 to clock frequency control DAC 22. While this circuit appears to have a feedback path from the output clock along lines 27 and 29, it should be appreciated that this frequency control circuit actually operates like an open-loop circuit, as the feedback clock signal merely serves to clock frequency control DAC 22, and does not act as an input to the circuit.
One element that consumes a significant amount of power is the VCTCXO. The power consumption is significant due to the requirement of maintaining the VCTCXO powered at all times when the terminal is powered on, particularly for TDMA systems, so that the terminal maintains an accurate time. A VCTCXO is required because the oscillator must be time and temperature stable to maintain an accurate time between calibration sequences. It also must have low-jitter to minimize the amount of phase noise introduced into the signal transmitted from the handset. The use of the high power consuming VCTCXO is a significant drawback of the circuit of FIG. 1.
Another prior art approach at reducing the power consumption of a wireless terminal is described in U.S. Pat. No. 5,416,425 to Nokia. The circuit described in the Nokia patent includes a high frequency local clock oscillator and a low frequency local clock oscillator. During a first step, the high frequency oscillator is calibrated to a received base station clock using an automatic frequency control (AFC) function. During a second step, an error between the high and low frequency clocks is measured. Based on the error, a selector selects one of the high and low frequency clocks for provision to a counter for time measurement. The amount of time the high frequency clock is provided to the counter depends on the error determined. Power is saved when the low frequency clock is provided to the counter for timing, by powering down the high frequency oscillator.
The Nokia approach suffers the drawbacks of: (1) requiring significant calibration time (it's a two-step approach); (2) complexity in implementation; and (3) limited accuracy.